projects / platform / upstream / llvm.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 23e3e10) | patch
[RISCV] Add IsSignExtendingOpW to the Zknh SHA256 instructions.
authorCraig Topper <craig.topper@sifive.com>
Wed, 14 Dec 2022 19:42:59 +0000 (11:42 -0800)
committerCraig Topper <craig.topper@sifive.com>
Wed, 14 Dec 2022 19:52:01 +0000 (11:52 -0800)
commit827fb6c38ca59236e634f69a497a71fe94e3e99b
tree218ff2bafa4066b25f512a166c0202a8d7dee83ctree | snapshot
parent23e3e107dceb1fd8c1fb81d1229f6aab09a1fce2commit | diff
[RISCV] Add IsSignExtendingOpW to the Zknh SHA256 instructions.

On RV64 these instructions produce a 32-bit value and sign extend
to 64-bits.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D140036
llvm/lib/Target/RISCV/RISCVInstrInfoZk.td diff | blob | history
llvm/test/CodeGen/RISCV/sextw-removal.ll diff | blob | history
Domain: System / Toolchain;