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(parent: 1c158d0) | patch
[mlir] Update various operations to declaratively specify their assembly format.
authorRiver Riddle <riddleriver@gmail.com>
Thu, 30 Jan 2020 19:31:50 +0000 (11:31 -0800)
committerRiver Riddle <riddleriver@gmail.com>
Thu, 30 Jan 2020 19:43:40 +0000 (11:43 -0800)
commit82170d5619987aac0de1f7cc62bdcdc8a68e783c
treee3277b984c427c342a278aa88ee8a64cb8670417tree | snapshot
parent1c158d0f90919ba19b8749556ac3a60e9d99a312commit | diff
[mlir] Update various operations to declaratively specify their assembly format.

Summary:
This revision switches over many operations to use the declarative methods for defining the assembly specification. This updates operations in the NVVM, ROCDL, Standard, and VectorOps dialects.

Differential Revision: https://reviews.llvm.org/D73407
mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td diff | blob | history
mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td diff | blob | history
mlir/include/mlir/Dialect/StandardOps/Ops.td diff | blob | history
mlir/include/mlir/Dialect/VectorOps/VectorOps.td diff | blob | history
mlir/include/mlir/IR/OpBase.td diff | blob | history
mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp diff | blob | history
mlir/lib/Dialect/LLVMIR/IR/ROCDLDialect.cpp diff | blob | history
mlir/lib/Dialect/StandardOps/Ops.cpp diff | blob | history
mlir/lib/Dialect/VectorOps/VectorOps.cpp diff | blob | history
mlir/test/Dialect/LLVMIR/invalid.mlir diff | blob | history
Domain: System / Toolchain;