[RISCV] Teach RISCVMatInt about cases where it can use LUI+SLLI to replace LUI+ADDI...
authorCraig Topper <craig.topper@sifive.com>
Tue, 20 Jul 2021 16:10:45 +0000 (09:10 -0700)
committerCraig Topper <craig.topper@sifive.com>
Tue, 20 Jul 2021 16:22:06 +0000 (09:22 -0700)
commit81efb825703c16ae659f3e17834ab011d06926e3
tree281df430e3121f75ff7489fcd3d44a28427147cf
parent2ad2c5d457bb625d93d9b9bf9c6d8bc7396334da
[RISCV] Teach RISCVMatInt about cases where it can use LUI+SLLI to replace LUI+ADDI+SLLI for large constants.

If we need to shift left anyway we might be able to take advantage
of LUI implicitly shifting its immediate left by 12 to cover part
of the shift. This allows us to use more bits of the LUI immediate
to avoid an ADDI.

isDesirableToCommuteWithShift now considers compressed instruction
opportunities when deciding if commuting should be allowed.

I believe this is the same or similar to one of the optimizations
from D79492.

Reviewed By: luismarques, arcbbb

Differential Revision: https://reviews.llvm.org/D105417
13 files changed:
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/test/CodeGen/RISCV/add-before-shl.ll
llvm/test/CodeGen/RISCV/double-mem.ll
llvm/test/CodeGen/RISCV/float-mem.ll
llvm/test/CodeGen/RISCV/half-mem.ll
llvm/test/CodeGen/RISCV/imm.ll
llvm/test/CodeGen/RISCV/rv64-large-stack.ll
llvm/test/CodeGen/RISCV/rv64zbp.ll
llvm/test/CodeGen/RISCV/rvv/constant-folding.ll
llvm/test/CodeGen/RISCV/urem-lkk.ll
llvm/test/MC/RISCV/rv64i-aliases-valid.s