clk: sunxi-ng: a83t: Support new timing mode for mmc2 clock
authorChen-Yu Tsai <wens@csie.org>
Mon, 24 Jul 2017 13:58:58 +0000 (21:58 +0800)
committerUlf Hansson <ulf.hansson@linaro.org>
Wed, 30 Aug 2017 12:01:48 +0000 (14:01 +0200)
commit81e911d0dcdb35203785542e0417cd8feb45df65
tree0d5ada4405b192bfa9e03017306f77ee9a81eae1
parentdc8797e39fca777217fd4cfc9c74a5337a3daa76
clk: sunxi-ng: a83t: Support new timing mode for mmc2 clock

The MMC2 clock supports a new timing mode. When the new mode is active,
the output clock rate is halved.

This patch sets the feature flag for the new timing mode, and adds
a pre-divider based on the mode bit.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
drivers/clk/sunxi-ng/ccu-sun8i-a83t.c