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[X86] Prefer lowerVectorShuffleAsBitMask over using a avx512 masked operation when...
authorCraig Topper <craig.topper@intel.com>
Fri, 30 Nov 2018 18:43:15 +0000 (18:43 +0000)
committerCraig Topper <craig.topper@intel.com>
Fri, 30 Nov 2018 18:43:15 +0000 (18:43 +0000)
commit8191307d0987ad1c18ae1cf391a43c4b54c2e41e
tree3e8301f710bbfb8d18666dc07139acd278787909tree | snapshot
parent4b5b0c0025c3238f7a8894ba1ac28b6f2394286acommit | diff
[X86] Prefer lowerVectorShuffleAsBitMask over using a avx512 masked operation when avx512bw/avx512vl is enabled.

This does require a constant pool load instead of loading an immediate into a gpr, moving to a k register and masking. But its less instructions and more consistent with previous ISAs. It probably opens up more combine opportunities as one of the test cases demonstrates.

llvm-svn: 348018
llvm/lib/Target/X86/X86ISelLowering.cpp diff | blob | history
llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll diff | blob | history
Domain: System / Toolchain;