drm/i915: Clarify VLV PLL p1 limits
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Tue, 24 Sep 2013 18:26:25 +0000 (21:26 +0300)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Thu, 10 Oct 2013 10:46:52 +0000 (12:46 +0200)
commit811bbf05447b17db2fb13387da9b7d553438d5c6
treebd4231488743512b78b7d0d1fff1f5af36095610
parent27e639bf024a0706015dbb348eb32619a9bb9329
drm/i915: Clarify VLV PLL p1 limits

For some reason there's a sort of off by one issue with the p1 divider.
The actual p1 limits according to
VLV2_DPLL_mphy_hsdpll_frequency_table_ww6_rev1p1.xlsm is 2-3, so we should
just say that instead of saying 1-3 and avoiding the 1 via the choice of
comparison operator.

I don't know why we're using different p1 limits for intel_limits_vlv_dac
and intel_limits_vlv_hdmi, but let's preserve that for now.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_display.c