Revert "[RISCV] Lower fixed length interleaved accesses via vssegN/vlsegN"
authorLuke Lau <luke@igalia.com>
Sun, 2 Apr 2023 14:56:02 +0000 (15:56 +0100)
committerLuke Lau <luke@igalia.com>
Sun, 2 Apr 2023 14:56:24 +0000 (15:56 +0100)
commit80f3be960355081935d21d6388c1442672a3c45f
tree2db6f9bf46e4dd64c3cc04226bdb5d2de3323410
parent9a99afb455601aaa3a28d307c7bbcfdaad3fa4fc
Revert "[RISCV] Lower fixed length interleaved accesses via vssegN/vlsegN"

This reverts commit b95913e8c3a3521b85d689a358e620d89a4e83de.
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.h
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
llvm/test/CodeGen/RISCV/O3-pipeline.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access-zve32x.ll [deleted file]
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll [deleted file]
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll
llvm/test/Transforms/InterleavedAccess/RISCV/interleaved-accesses.ll [deleted file]
llvm/test/Transforms/InterleavedAccess/RISCV/zve32x.ll [deleted file]
llvm/test/Transforms/InterleavedAccess/RISCV/zvl32b.ll [deleted file]