[X86][Costmodel] Load/store i32/f32 Stride=2 VF=16 interleaving costs
authorRoman Lebedev <lebedev.ri@gmail.com>
Fri, 1 Oct 2021 13:52:51 +0000 (16:52 +0300)
committerRoman Lebedev <lebedev.ri@gmail.com>
Fri, 1 Oct 2021 14:48:14 +0000 (17:48 +0300)
commit80cd8da78d027f59b54586887af4bb9c3b36a6ba
treec299a9576425e13f28c649cae52ab1ed9a6797ea
parent3a0643e9c2252290a9f29c2b3ceb696033af4903
[X86][Costmodel] Load/store i32/f32 Stride=2 VF=16 interleaving costs

The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3

For load we have:
https://godbolt.org/z/M9eev3xe8 - for intels `Block RThroughput: =8.0`; for ryzens, `Block RThroughput: <=4.0`
So pick cost of `8`.

For store we have:
https://godbolt.org/z/M9eev3xe8 - for intels `Block RThroughput: =8.0`; for ryzens, `Block RThroughput: =4.0`
So pick cost of `8`.

I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D110756
llvm/lib/Target/X86/X86TargetTransformInfo.cpp
llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-2.ll
llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-2.ll
llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-2.ll
llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-2.ll