review.tizen.org Git - platform/upstream/llvm.git/commit

projects / platform / upstream / llvm.git / commit

author	Hsiangkai Wang <kai.wang@sifive.com>
	Tue, 5 Oct 2021 06:20:36 +0000 (14:20 +0800)
committer	Hsiangkai Wang <kai.wang@sifive.com>
	Tue, 5 Oct 2021 13:49:54 +0000 (21:49 +0800)
commit	80a645630660b1096aa16e18ed4747b24995f6cb
tree	091cc8c184f94c4f411e3ac4b839fbae1ad52ee4	tree \| snapshot
parent	83e074a0c652a668c8a5d572f8c77b58c8383ff0	commit \| diff

[RISCV] Update to vlm.v and vsm.v according to v1.0-rc1.

vle1.v -> vlm.v
vse1.v -> vsm.v

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D106044

42 files changed:

clang/include/clang/Basic/riscv_vector.td		diff \| blob \| history
clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vse.c		diff \| blob \| history
clang/test/CodeGen/RISCV/rvv-intrinsics/vle.c		diff \| blob \| history
clang/test/CodeGen/RISCV/rvv-intrinsics/vse.c		diff \| blob \| history
llvm/include/llvm/IR/IntrinsicsRISCV.td		diff \| blob \| history
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp		diff \| blob \| history
llvm/lib/Target/RISCV/RISCVInstrInfoV.td		diff \| blob \| history
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td		diff \| blob \| history
llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td		diff \| blob \| history
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/extload-truncstore.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-load-store.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-logic.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/load-mask.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/unaligned-loads-stores.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vle1-rv32.ll	[deleted file]	blob \| history
llvm/test/CodeGen/RISCV/rvv/vle1-rv64.ll	[deleted file]	blob \| history
llvm/test/CodeGen/RISCV/rvv/vlm-rv32.ll	[new file with mode: 0644]	blob
llvm/test/CodeGen/RISCV/rvv/vlm-rv64.ll	[new file with mode: 0644]	blob
llvm/test/CodeGen/RISCV/rvv/vse1-rv32.ll	[deleted file]	blob \| history
llvm/test/CodeGen/RISCV/rvv/vse1-rv64.ll	[deleted file]	blob \| history
llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv32.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv64.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vsm-rv32.ll	[new file with mode: 0644]	blob
llvm/test/CodeGen/RISCV/rvv/vsm-rv64.ll	[new file with mode: 0644]	blob
llvm/test/MC/RISCV/rvv/aliases.s		diff \| blob \| history
llvm/test/MC/RISCV/rvv/load.s		diff \| blob \| history
llvm/test/MC/RISCV/rvv/store.s		diff \| blob \| history

Domain: System / Toolchain;

RSS Atom