drm/amdgpu: refine uvd 5.0 clock gate feature.
authorRex Zhu <Rex.Zhu@amd.com>
Tue, 8 Nov 2016 12:43:50 +0000 (20:43 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 11 Nov 2016 15:21:11 +0000 (10:21 -0500)
commit809a6a62b6b3e688e6b4d57acf296d6f25620c8a
tree67f7c50e2c4fa52c46ed2c30e58b2b36ebf60c79
parent68260f340e191a67056b6c27f958f09029b9e11f
drm/amdgpu: refine uvd 5.0 clock gate feature.

1. fix uvd cg status not correct.
2. fix uvd pg can't work on tonga.
3. enable uvd mgcg.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c