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(parent: 9d6dfd2) | patch
upstream: [media] mt9p031: Add support for PLL bypass
authorLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Sun, 9 Feb 2014 20:31:47 +0000 (17:31 -0300)
committerChanho Park <chanho61.park@samsung.com>
Tue, 18 Nov 2014 02:54:41 +0000 (11:54 +0900)
commit80553bca3f30dcdda2055c6de851f353c7f4bafe
tree2bc7c86609d5d657ed1339a41cdeabe20f55723etree | snapshot
parent9d6dfd21317c38ce9fe9b858fada2ca1848011f9commit | diff
upstream: [media] mt9p031: Add support for PLL bypass

When the input clock frequency is out of bounds for the PLL, bypass the
PLL and just divide the input clock to achieve the requested output
frequency.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>
drivers/media/i2c/mt9p031.c diff | blob | history
Domain: System / Kernel;