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(parent: c8ea836) | patch
firmware: Not to clear all the MIP
authorNick Hu <nick.hu@sifive.com>
Tue, 17 Jan 2023 08:14:27 +0000 (16:14 +0800)
committerAnup Patel <anup@brainfault.org>
Wed, 8 Feb 2023 05:09:20 +0000 (10:39 +0530)
commit8050081f68b2b66f8937b15a6753ec6408c2fdee
tree1af715441c6e1e628c6d3a711c00bdbf6991a8f2tree | snapshot
parentc8ea836ee33eb778f48f780412e147386dac5301commit | diff
firmware: Not to clear all the MIP

In generic behavior of QEMU, if the pending bits of PLIC are still set and
we clear the SEIP, the QEMU may not set the SEIP back immediately and the
interrupt may not be handled anymore until the new interrupts arrived and
QEMU set the SEIP back which is a generic behavior in QEMU.

Signed-off-by: Nick Hu <nick.hu@sifive.com>
Signed-off-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
firmware/fw_base.S diff | blob | history
Domain: System / Kernel;