dt-bindings: clock: Add StarFive JH7110 system clock and reset generator
authorEmil Renner Berthing <kernel@esmil.dk>
Sat, 1 Apr 2023 11:19:13 +0000 (19:19 +0800)
committerConor Dooley <conor.dooley@microchip.com>
Wed, 5 Apr 2023 14:43:15 +0000 (15:43 +0100)
commit7fce1e39f01900a294cd2c456c77f3e2512e0634
tree85f891edba674cfb16bf38d621b4bd19e8f1b390
parenteeac8ede17557680855031c6f305ece2378af326
dt-bindings: clock: Add StarFive JH7110 system clock and reset generator

Add bindings for the system clock and reset generator (SYSCRG) on the
JH7110 RISC-V SoC by StarFive Ltd.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml [new file with mode: 0644]
include/dt-bindings/clock/starfive,jh7110-crg.h [new file with mode: 0644]
include/dt-bindings/reset/starfive,jh7110-crg.h [new file with mode: 0644]