powerpc/85xx: Rework P2020DS device tree
authorKumar Gala <galak@kernel.crashing.org>
Wed, 26 Oct 2011 13:35:24 +0000 (08:35 -0500)
committerKumar Gala <galak@kernel.crashing.org>
Thu, 24 Nov 2011 08:01:38 +0000 (02:01 -0600)
commit7f9ce7143efe1231d66a5c91e57fce55fce6728e
tree148cd9eb3003efad9e6880159081aa8e02581a51
parentb0e2f248b4ed6aea3191c3419e6f70407d53d8d8
powerpc/85xx: Rework P2020DS device tree

Utilize new split between board & SoC, and new SoC device trees split
into pre & post utilizing 'template' includes for SoC IP blocks.

Other changes include:

* Moved to specifying interrupt-parent for mpic at root
* Moved to 4-cell mpic interrupt cells to support MPIC timers
* Reworked PCIe nodes to allow supportin IRQs for controller (errors)
  and moved PCI device IRQs down to virtual bridge level
* Updated spi node to new espi binding specification
* Renamed 'sdhci' node to 'sdhc'
* Changed GPIO compatiable from 'fsl,mpc8572-gpio' to 'fsl,pq3-gpio' as the
 'mpc8572' compatiable is to deal with a 'mpc8572' specific to an erratum
* Fixed wrong reg offsets for mdio nodes associated with etsec2 & etsec3
* Dropping "fsl,p2020-IP..." from compatibles for standard blocks

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
arch/powerpc/boot/dts/fsl/p2020si-post.dtsi [new file with mode: 0644]
arch/powerpc/boot/dts/fsl/p2020si-pre.dtsi [new file with mode: 0644]
arch/powerpc/boot/dts/p2020ds.dts
arch/powerpc/boot/dts/p2020ds.dtsi [new file with mode: 0644]
arch/powerpc/boot/dts/p2020si.dtsi