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(parent: d056d5d) | patch
[RISCV] Remove unneeded indexed segment load/store vector pseudo instruction.
authorCraig Topper <craig.topper@sifive.com>
Fri, 19 Feb 2021 18:28:45 +0000 (10:28 -0800)
committerCraig Topper <craig.topper@sifive.com>
Fri, 19 Feb 2021 18:28:48 +0000 (10:28 -0800)
commit7f5b3886e41ca0ff9e4275e515bd6dde576ead35
treef845b65c9ec2ac8e9b38ce93adaf302df5d9ecbbtree | snapshot
parentd056d5decfb593cfc53b421a89075d2063f76ec9commit | diff
[RISCV] Remove unneeded indexed segment load/store vector pseudo instruction.

We had more combinations of data and index lmuls than we needed.

Also add some asserts to verify that the IndexVT and data VT have
the same element count when we isel these pseudo instructions.
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp diff | blob | history
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td diff | blob | history
Domain: System / Toolchain;