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[NFC][Codegen][X86][AArch64] Add "(x s% C) == 0" tests
authorRoman Lebedev <lebedev.ri@gmail.com>
Sat, 20 Jul 2019 19:25:44 +0000 (19:25 +0000)
committerRoman Lebedev <lebedev.ri@gmail.com>
Sat, 20 Jul 2019 19:25:44 +0000 (19:25 +0000)
commit7f0c23576f5224181098e37781c7a82dff224b19
treedb37cc765b451d2158088d21e16bab23e48ca6d7tree | snapshot
parente97f2f33e757a639492c4f5295ec825fb1685294commit | diff
[NFC][Codegen][X86][AArch64] Add "(x s% C) == 0" tests

Much like with `urem`, the same optimization (albeit with slightly
different algorithm) applies for the signed case, too.

I'm simply copying the test coverage from `urem` case for now,
i believe it should be (close to?) sufficient.

llvm-svn: 366640
llvm/test/CodeGen/AArch64/srem-seteq-optsize.ll [new file with mode: 0644] blob
llvm/test/CodeGen/AArch64/srem-seteq-vec-nonsplat.ll [new file with mode: 0644] blob
llvm/test/CodeGen/AArch64/srem-seteq-vec-splat.ll [new file with mode: 0644] blob
llvm/test/CodeGen/AArch64/srem-seteq.ll [new file with mode: 0644] blob
llvm/test/CodeGen/X86/srem-seteq-optsize.ll [new file with mode: 0644] blob
llvm/test/CodeGen/X86/srem-seteq-vec-nonsplat.ll [new file with mode: 0644] blob
llvm/test/CodeGen/X86/srem-seteq-vec-splat.ll [new file with mode: 0644] blob
llvm/test/CodeGen/X86/srem-seteq.ll [new file with mode: 0644] blob
Domain: System / Toolchain;