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MIPS: Perf: Fix 74K cache map
authorDeng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Tue, 8 Oct 2013 15:17:48 +0000 (16:17 +0100)
committerRalf Baechle <ralf@linux-mips.org>
Tue, 29 Oct 2013 20:18:23 +0000 (21:18 +0100)
commit7f081f175502373673c015a4d0fa1d5cc264758a
treebd53f2a1470b37b79d7e5f5f6e0fe7bcfbc452d4tree | snapshot
parent959f58544b7f20c92d5eb43d1232c96c15c01bfbcommit | diff
MIPS: Perf: Fix 74K cache map

According to Software User's Manual, the event of last-level-cache
read/write misses is mapped to even counters. Odd counters of that
event number count miss cycles.

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6036/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/kernel/perf_event_mipsxx.c diff | blob | history
Domain: SDK / Emulator;