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(parent: 98ee8b2) | patch
clk: renesas: r9a07g044: Add mux and divider for G clock
authorBiju Das <biju.das.jz@bp.renesas.com>
Fri, 3 Dec 2021 11:51:50 +0000 (11:51 +0000)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Wed, 8 Dec 2021 09:05:56 +0000 (10:05 +0100)
commit7ef9c45a23a9071dee23ca1a769c53ec2cdc07c0
treea38469ad418a14f0f444d18abb418bf861767b1atree | snapshot
parent98ee8b2f66ebff2fafe85668b9d00c3433b76566commit | diff
clk: renesas: r9a07g044: Add mux and divider for G clock

G clock is sourced from PLL3 and PLL6. The output of the mux is
connected to divider.

This patch adds a mux and divider for getting different rates from
this clock sources.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211203115154.31864-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/r9a07g044-cpg.c diff | blob | history
drivers/clk/renesas/rzg2l-cpg.h diff | blob | history
Domain: System / Kernel;