[ARM] Introduce separate features for FP registers
authorSjoerd Meijer <sjoerd.meijer@arm.com>
Thu, 30 May 2019 12:37:05 +0000 (12:37 +0000)
committerSjoerd Meijer <sjoerd.meijer@arm.com>
Thu, 30 May 2019 12:37:05 +0000 (12:37 +0000)
commit7eb95d672dbf302a422ae4dbb24dd7cc583b65df
tree9224450e0c07a654fb78cfdb755b83f592dfdcb9
parentce127bb60ea1d570e50a6730b468ba537fd08751
[ARM] Introduce separate features for FP registers

The MVE extension in Arm v8.1-M permits the use of some move, load and
store isntructions which access the FP registers, even if there's no
actual FP support in the processor (in particular, if you have the
integer-only version of MVE).

Therefore, we need separate subtarget features to condition those
instructions on, which are implied by both FP and MVE but are not part
of either.

Patch mostly by Simon Tatham.

Differential Revision: https://reviews.llvm.org/D60694

llvm-svn: 362088
llvm/lib/Target/ARM/ARM.td
llvm/lib/Target/ARM/ARMInstrNEON.td
llvm/lib/Target/ARM/ARMInstrVFP.td
llvm/lib/Target/ARM/ARMPredicates.td
llvm/lib/Target/ARM/ARMSubtarget.h
llvm/test/MC/ARM/fullfp16-neg.s
llvm/test/MC/ARM/mve-fp-registers.s [new file with mode: 0644]
llvm/test/MC/ARM/single-precision-fp.s
llvm/test/MC/ARM/vmrs_vmsr.s