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(parent: dec206a) | patch
clk: versal: Fix watchdog clock issue
authorT Karthik Reddy <t.karthik.reddy@xilinx.com>
Thu, 9 Apr 2020 03:34:54 +0000 (21:34 -0600)
committerMichal Simek <michal.simek@xilinx.com>
Mon, 27 Apr 2020 11:57:17 +0000 (13:57 +0200)
commit7eab624baf96a6d967416ffeb51e3fef289c47ae
tree498ac555035d59437cb95c80cbf70399f3dc7e5etree | snapshot
parentdec206a09b660ee1ac58e3cd9a7b2003aeca4381commit | diff
clk: versal: Fix watchdog clock issue

Enable mux based clocks to populate LPD_LSBUS clock to xilinx_wwdt
driver. Skip reading clock rate for the mux based clocks with
parent clock id is zero.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
drivers/clk/clk_versal.c diff | blob | history
Domain: System / Kernel;