PR middle-end/80270: ICE in extract_bit_field_1
authorRoger Sayle <roger@nextmovesoftware.com>
Mon, 28 Feb 2022 22:26:43 +0000 (22:26 +0000)
committerRoger Sayle <roger@nextmovesoftware.com>
Mon, 28 Feb 2022 22:26:43 +0000 (22:26 +0000)
commit7e5c6edeb1b2339e10f10bee270e61dbad985800
tree911a7daf527e95a1ee9e866ff1f3c5afd8840562
parentec1b9ba2d7913fe5e9deacc8e55e7539262f5124
PR middle-end/80270: ICE in extract_bit_field_1

This patch fixes PR middle-end/80270, an ICE-on-valid regression, where
performing a bitfield extraction on a variable explicitly stored in a
hard register by the user causes a segmentation fault during RTL
expansion.  Nearly identical source code without the "asm" qualifier
compiles fine.  The point of divergence is in simplify_gen_subreg
which tries to avoid creating non-trivial SUBREGs of hard registers,
to avoid problems during register allocation.  This suggests the
simple solution proposed here, to copy hard registers to a new pseudo
in extract_integral_bit_field, just before calling simplify_gen_subreg.

2022-02-28  Roger Sayle  <roger@nextmovesoftware.com>
    Eric Botcazou  <ebotcazou@adacore.com>

gcc/ChangeLog
PR middle-end/80270
* expmed.cc (extract_integral_bit_field): If OP0 is a hard
register, copy it to a pseudo before calling simplify_gen_subreg.

gcc/testsuite/ChangeLog
* gcc.target/i386/pr80270.c: New test case.
gcc/expmed.cc
gcc/testsuite/gcc.target/i386/pr80270.c [new file with mode: 0644]