Exynos542x: add L2 control register configuration
authorAkshay Saraswat <akshay.s@samsung.com>
Fri, 20 Feb 2015 07:57:17 +0000 (13:27 +0530)
committerMinkyu Kang <mk7.kang@samsung.com>
Sat, 28 Feb 2015 09:03:46 +0000 (18:03 +0900)
commit7e514eef02d2508a19be13d3efdf747c4e7ef5c5
treeaff4796e19e86f23d01e1392961984740cb1da6d
parentf0f76b0a4c7181b2cbde39ec04eac8973cd4ad1f
Exynos542x: add L2 control register configuration

This patch does 3 things:
1. Enables ECC by setting 21st bit of L2CTLR.
2. Restore data and tag RAM latencies to 3 cycles because iROM sets
   0x3000400 L2CTLR value during switching.
3. Disable clean/evict push to external by setting 3rd bit of L2ACTLR.
   We need to restore this here due to switching.

Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
arch/arm/cpu/armv7/exynos/lowlevel_init.c
arch/arm/cpu/armv7/exynos/soc.c