aarch64: Add missing movmisalign patterns
authorRichard Sandiford <richard.sandiford@arm.com>
Thu, 3 Feb 2022 10:44:00 +0000 (10:44 +0000)
committerRichard Sandiford <richard.sandiford@arm.com>
Thu, 3 Feb 2022 10:44:00 +0000 (10:44 +0000)
commit7e4f89a23e32604f71f8f6756c8856bf07bf7ac2
treeed93c9ad662aac4ca6cea855a66105e359ac3646
parent6a770526600a7ffda1f288fa481a4322d5f149b4
aarch64: Add missing movmisalign patterns

The Advanced SIMD movmisalign patterns didn't handle 16-bit
FP modes, which meant that the vector loop for:

  void
  test (_Float16 *data)
  {
    _Pragma ("omp simd")
    for (int i = 0; i < 8; ++i)
      data[i] = 1.0;
  }

would be versioned for alignment.

This was causing some new failures in aarch64/sve/single_5.c:

FAIL: gcc.target/aarch64/sve/single_5.c scan-assembler-not \\tb
FAIL: gcc.target/aarch64/sve/single_5.c scan-assembler-not \\tcmp
FAIL: gcc.target/aarch64/sve/single_5.c scan-assembler-times \\tstr\\tq[0-9]+, 10

but I didn't look into what changed from earlier releases.
Adding the missing modes removes some existing xfails.

gcc/
* config/aarch64/aarch64-simd.md (movmisalign<mode>): Extend from
VALL to VALL_F16.

gcc/testsuite/
* gcc.target/aarch64/sve/single_5.c: Remove some XFAILs.
gcc/config/aarch64/aarch64-simd.md
gcc/testsuite/gcc.target/aarch64/sve/single_5.c