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drm/amdgpu: Program GC registers through RLCG interface in gfx_v11/gmc_v11
authorYifan Zha <Yifan.Zha@amd.com>
Wed, 7 Sep 2022 06:13:02 +0000 (14:13 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 18 Oct 2022 18:52:06 +0000 (14:52 -0400)
commit7e2c58320ed59c9326e82cf9c00090f6a912fb64
tree28af081efa42382cce3e553a5f7d5e1c1d0f547ctree | snapshot
parentb3372fa74d2a7f840bea706607ee2224dfd24039commit | diff
drm/amdgpu: Program GC registers through RLCG interface in gfx_v11/gmc_v11

[Why]
L1 blocks most of GC registers accessing by MMIO.

[How]
Use RLCG interface to program GC registers under SRIOV VF in full access time.

Signed-off-by: Yifan Zha <Yifan.Zha@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c diff | blob | history
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c diff | blob | history
drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c diff | blob | history
Domain: System / Kernel;