[ARM] Fix assembly and disassembly for VMRS/VMSR
authorAndre Vieira <andre.simoesdiasvieira@arm.com>
Mon, 7 Aug 2017 08:41:05 +0000 (08:41 +0000)
committerAndre Vieira <andre.simoesdiasvieira@arm.com>
Mon, 7 Aug 2017 08:41:05 +0000 (08:41 +0000)
commit7dffb9bfa6087ce519f730eb6ab41a204f481a40
treed17f4af164bd8de84b3c8f04d58f817eadff77ea
parent5d432ec929031da10cbbde65fa438b9f3d7356c9
[ARM] Fix assembly and disassembly for VMRS/VMSR

This patch addresses two issues with assembly and disassembly for VMRS/VMSR:

1.currently VMRS/VMSR instructions accessing fpsid, mvfr{0-2} and fpexc, are
  accepted for non ARMv8-A targets.

2. all VMRS/VMSR instructions accept writing/reading to PC and SP, when only
   ARMv7-A and ARMv8-A should be allowed to write/read to SP and none to PC.

This patch addresses those issues and adds tests for these cases.

Differential Revision: https://reviews.llvm.org/D36306

llvm-svn: 310243
llvm/lib/Target/ARM/ARMInstrVFP.td
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
llvm/test/MC/ARM/directive-arch_extension-fp.s
llvm/test/MC/ARM/simple-fp-encoding.s
llvm/test/MC/ARM/vmrs_vmsr.s [new file with mode: 0644]
llvm/test/MC/Disassembler/ARM/arm-vmrs_vmsr.txt [new file with mode: 0644]
llvm/test/MC/Disassembler/ARM/fp-encoding.txt
llvm/test/MC/Disassembler/ARM/thumb-vmrs_vmsr.txt [new file with mode: 0644]