RISC-V: Change variable type for 32-bit compatible
authorZong Li <zong@andestech.com>
Mon, 25 Jun 2018 08:49:40 +0000 (16:49 +0800)
committerPalmer Dabbelt <palmer@sifive.com>
Wed, 4 Jul 2018 20:56:52 +0000 (13:56 -0700)
commit7df85002178e708aa749c63020fd333d9f085ced
tree65bacd8591ee07fd052f8c660232cc118f946f72
parentc480d8911fda96a0f37634bd4dc4e2c8a87c38da
RISC-V: Change variable type for 32-bit compatible

Signed-off-by: Zong Li <zong@andestech.com>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
arch/riscv/kernel/module.c