clk: samsung: Add CLK_SET_RATE_PARENT to some AUDSS CLK CON clocks
authorSylwester Nawrocki <s.nawrocki@samsung.com>
Mon, 17 Jul 2017 12:39:21 +0000 (14:39 +0200)
committerSylwester Nawrocki <s.nawrocki@samsung.com>
Wed, 9 Aug 2017 15:17:04 +0000 (17:17 +0200)
commit7df45a532c5ee3efe106e8a9042a3524b0b587b1
tree138b08398b57f7cb900eb5f85ceaf0f66aa03c2a
parent41097f25e9b2091d5d0a309cceb788704f21e1d2
clk: samsung: Add CLK_SET_RATE_PARENT to some AUDSS CLK CON clocks

This allows clk rate propagation up to the clock tree so EPLL
can be reprogrammed indirectly when setting rate of the Audio
Subsystem clocks.
The advantage is that sound machine driver can operate only
on the leaf clocks rather than explicitly re-configuring
the root clock (EPLL).

Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
drivers/clk/samsung/clk-exynos-audss.c