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[RISCV] Add support for floating point registers in inlineasm
authorSimon Cook <simon.cook@embecosm.com>
Wed, 31 Jul 2019 09:12:00 +0000 (09:12 +0000)
committerSimon Cook <simon.cook@embecosm.com>
Wed, 31 Jul 2019 09:12:00 +0000 (09:12 +0000)
commit7deaeee753f60ce4ef4ee7fda9d95fe5941b4ffb
treeabd57772e1f0f883122a24f5c66c05e2c7b42289tree | snapshot
parent1518c88a7d440a29b13ff6ba49b300c0bf53c187commit | diff
[RISCV] Add support for floating point registers in inlineasm

This adds support for parsing/emitting in IR the floating-point RISC-V
registers in inline assembly clobber lists.

Differential Revision: https://reviews.llvm.org/D64737

llvm-svn: 367399
clang/lib/Basic/Targets/RISCV.cpp diff | blob | history
clang/test/Sema/riscv-asm.c [new file with mode: 0644] blob
Domain: System / Toolchain;