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riscv: dts: renesas: rzfive-smarc-som: Drop PHY interrupt support for ETH{0,1}
authorLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Mon, 2 Jan 2023 22:27:08 +0000 (22:27 +0000)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Thu, 26 Jan 2023 15:02:16 +0000 (16:02 +0100)
commit7dd48e96d0cda9af79a2fee85e9135b4781f9ee1
tree240fb2f6461056c8ca615f20034d92b3911cb331tree | snapshot
parent87d85b48f8109980c83b57b37ba963949ffbef25commit | diff
riscv: dts: renesas: rzfive-smarc-som: Drop PHY interrupt support for ETH{0,1}

IRQC support for RZ/Five is still missing so drop the interrupts and
interrupt-parent properties from the PHY nodes of ETH{0,1}.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230102222708.274369-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi diff | blob | history
Domain: System / Kernel;