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[GlobalISel][AArch64] Add instruction selection support for G_FCOS and G_FSIN
authorJessica Paquette <jpaquette@apple.com>
Mon, 28 Jan 2019 18:34:18 +0000 (18:34 +0000)
committerJessica Paquette <jpaquette@apple.com>
Mon, 28 Jan 2019 18:34:18 +0000 (18:34 +0000)
commit7db82d7257f9a2793858159f96dc65e117b27918
tree75c089fdc9d8c9caab069712e12eb86e0c4c8234tree | snapshot
parent296f19b3d99fe147d714fe84000fd49ea3b9987dcommit | diff
[GlobalISel][AArch64] Add instruction selection support for G_FCOS and G_FSIN

This contains all of the legalizer changes from D57197 necessary to select
G_FCOS and G_FSIN. It also updates several existing IR tests in
test/CodeGen/AArch64 that verify that we correctly lower the G_FCOS and G_FSIN
instructions.

https://reviews.llvm.org/D57197
3/3

llvm-svn: 352402
llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp diff | blob | history
llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp diff | blob | history
llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp diff | blob | history
llvm/test/CodeGen/AArch64/GlobalISel/legalize-cos.mir [new file with mode: 0644] blob
llvm/test/CodeGen/AArch64/GlobalISel/legalize-sin.mir [new file with mode: 0644] blob
llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir diff | blob | history
llvm/test/CodeGen/AArch64/arm64-vfloatintrinsics.ll diff | blob | history
llvm/test/CodeGen/AArch64/f16-instructions.ll diff | blob | history
llvm/test/CodeGen/AArch64/sincospow-vector-expansion.ll diff | blob | history
Domain: System / Toolchain;