pan/mdg: Fix 2-const CSEL at block beginning
authorAlyssa Rosenzweig <alyssa@rosenzweig.io>
Fri, 30 Jun 2023 20:05:58 +0000 (16:05 -0400)
committerAlyssa Rosenzweig <alyssa@rosenzweig.io>
Fri, 30 Jun 2023 20:29:35 +0000 (16:29 -0400)
commit7da1e4c326d9f3213060c45ddeb1c65afcba7bff
tree914a773b74a234a49ffe6eaddf45ea451747c179
parentb66b122e0376bfbc81e167141e46f92384869dcc
pan/mdg: Fix 2-const CSEL at block beginning

mir_prev_op will point to the last instruction of the block in that case because
the block instruction list is circular. That would cause an invald
write-after-read relationship between the move we insert with the constants and
the CSEL reading them, which DCE "helpfully" optimizes out, leaving a read from
an undefined def. That ends up getting RA'd to an invalid register.

All in all, pretty bad.

Identified due to a new assert fail after the proper temp_count fix.

Affects dEQP-GLES31.functional.separate_shader.random.12.

No shader-db changes.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Italo Nicola <italonicola@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23769>
src/panfrost/midgard/midgard_compile.c