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(parent: eee617a) | patch
sh_eth: Ensure proper ordering of descriptor active bit write/read
authorBen Hutchings <ben.hutchings@codethink.co.uk>
Tue, 3 Mar 2015 00:52:00 +0000 (00:52 +0000)
committerDavid S. Miller <davem@davemloft.net>
Tue, 3 Mar 2015 02:30:56 +0000 (21:30 -0500)
commit7d7355f58ba4f9d68d2fb79864bab4ccb618e4e1
tree79a7efdc9a433f1c5f05651adc70c2579760c313tree | snapshot
parenteee617a1c35dbf598690879f13dc3df548fd6ea6commit | diff
sh_eth: Ensure proper ordering of descriptor active bit write/read

When submitting a DMA descriptor, the active bit must be written last.
When reading a completed DMA descriptor, the active bit must be read
first.

Add memory barriers to ensure that this ordering is maintained.

Signed-off-by: Ben Hutchings <ben.hutchings@codethink.co.uk>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/renesas/sh_eth.c diff | blob | history
Domain: System / Kernel;