[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
authorHsiangkai Wang <kai.wang@sifive.com>
Thu, 2 Sep 2021 14:42:50 +0000 (22:42 +0800)
committerHsiangkai Wang <kai.wang@sifive.com>
Fri, 24 Sep 2021 09:09:50 +0000 (17:09 +0800)
commit7d39a8a92122e56b014e41606bf15623971d15ff
tree09c66169d270f308b80e0ca0efb047c743013864
parentdade83c02a11401897bcdb8c255db69b5c366e95
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.

Add the tail policy argument to LLVM IR intrinsics. There are two policies for tail elements. Tail agnostic means users do not care about the values in the tail elements and tail undisturbed means the values in the tail elements need to be kept after the operation. In order to let users control the tail policy, we add an additional argument at the end of the argument list.

For unmasked operations, we have no maskedoff and the tail policy is always tail agnostic. If users want to keep tail elements under unmasked operations, they could use all one mask in the masked operations to do it. So, we only add the additional argument for masked operations for most cases. There are exceptions listed below.

In this patch, we do not handle the following cases to reduce the complexity of the patch. There could be two separate patches for them.

* Use dest argument to control tail policy
vmerge.vvm/vmerge.vxm/vmerge.vim (add _t builtins with additional dest argument)
vfmerge.vfm (add _t builtins with additional dest argument)
vmv.v.v (add _t builtins with additional dest argument)
vmv.v.x (add _t builtins with additional dest argument)
vmv.v.i (add _t builtins with additional dest argument)
vfmv.v.f (add _t builtins with additional dest argument)
vadc.vvm/vadc.vxm/vadc.vim (add _t builtins with additional dest argument)
vsbc.vvm/vsbc.vxm (add _t builtins with additional dest argument)

* Always has tail argument for masked/unmasked intrinsics
Vector Single-Width Integer Multiply-Add Instructions (add _t and _mt builtins)
Vector Widening Integer Multiply-Add Instructions (add _t and _mt builtins)
Vector Single-Width Floating-Point Fused Multiply-Add Instructions (add _t and _mt builtins)
Vector Widening Floating-Point Fused Multiply-Add Instructions (add _t and _mt builtins)
Vector Reduction Operations (add _t and _mt builtins)
Vector Slideup Instructions (add _t and _mt builtins)
Vector Slidedown Instructions (add _t and _mt builtins)

Discussion: https://github.com/riscv/rvv-intrinsic-doc/pull/101

Differential Revision: https://reviews.llvm.org/D105092
232 files changed:
llvm/include/llvm/IR/IntrinsicsRISCV.td
llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
llvm/test/CodeGen/RISCV/rvv/common-shuffle-patterns.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
llvm/test/CodeGen/RISCV/rvv/interleave-crash.ll
llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/tail-agnostic-impdef-copy.mir
llvm/test/CodeGen/RISCV/rvv/vaadd-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vaadd-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vaaddu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vaaddu-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vadd-policy.ll [new file with mode: 0644]
llvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vadd-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vand-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vasub-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vasub-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vasubu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vasubu-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vdiv-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vdiv-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vdivu-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfadd-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfadd-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-x-f-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-x-f-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfdiv-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfdiv-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfmax-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfmax-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfmin-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfmin-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfmul-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfmul-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfrdiv-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfrdiv-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfrec7-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfrec7-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfrsqrt7-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfrsqrt7-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfrsub-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfrsub-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfsqrt-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfsqrt-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfsub-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfsub-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfwadd-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfwadd-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfwmul-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfwmul-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfwsub-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfwsub-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vle-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vle-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vleff-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vleff-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vloxei-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vloxei-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vlse-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vlse-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32-dead.ll
llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll
llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vluxei-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vluxei-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vmax-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmax-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vmaxu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmaxu-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vmin-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmin-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vminu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vminu-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vmul-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmul-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vmulh-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmulh-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vmulhu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmulhu-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vnclip-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vnclip-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vnclipu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vnclipu-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vnsra-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vnsra-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vnsrl-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vnsrl-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vor-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vor-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vrem-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vrem-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vremu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vremu-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vrsub-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vrsub-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vsadd-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vsadd-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vsaddu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vsaddu-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
llvm/test/CodeGen/RISCV/rvv/vsext-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vsext-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vslide1down-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vslide1down-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vslide1up-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vslide1up-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vsll-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vsll-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vsmul-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vsra-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vsra-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vsrl-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vsrl-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vssra-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vssra-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vssrl-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vssrl-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vssub-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vssub-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vssubu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vssubu-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vsub-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vsub-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vwadd-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vwadd-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vwaddu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vwaddu-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vwmul-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vwmul-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vwmulsu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vwmulsu-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vwmulu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vwmulu-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vwsub-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vwsub-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vwsubu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vwsubu-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vxor-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vxor-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vzext-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vzext-rv64.ll
llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll