pinctrl: aspeed: Read and write bits in LPC and GFX controllers
authorAndrew Jeffery <andrew@aj.id.au>
Tue, 20 Dec 2016 07:35:48 +0000 (18:05 +1030)
committerLinus Walleij <linus.walleij@linaro.org>
Tue, 27 Dec 2016 22:15:32 +0000 (23:15 +0100)
commit7d29ed88acbbf00e2056634bd4c0172d55d2568c
tree8a12e5e5e3d359d60acf6a04ea00f7be9b747686
parentc95b0fec3cff0ba584fd2f9e71fd9001ad15381a
pinctrl: aspeed: Read and write bits in LPC and GFX controllers

The System Control Unit IP block in the Aspeed SoCs is typically where
the pinmux configuration is found, but not always. A number of pins
depend on state in one of LPC Host Control (LHC) or SoC Display
Controller (GFX) IP blocks, so the Aspeed pinmux drivers should have the
means to adjust these as necessary.

We use syscon to cast a regmap over the GFX and LPC blocks, which is
used as an arbitration layer between the relevant driver and the pinctrl
subsystem. The regmaps are then exposed to the SoC-specific pinctrl
drivers by phandles in the devicetree, and are selected during a mux
request by querying a new 'ip' member in struct aspeed_sig_desc.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c
drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
drivers/pinctrl/aspeed/pinctrl-aspeed.c
drivers/pinctrl/aspeed/pinctrl-aspeed.h