radv: fix dynamic RT stack size with VGPR spilling
authorRhys Perry <pendingchaos02@gmail.com>
Mon, 14 Feb 2022 19:23:15 +0000 (19:23 +0000)
committerMarge Bot <emma+marge@anholt.net>
Tue, 20 Sep 2022 01:39:20 +0000 (01:39 +0000)
commit7d26fafacf3e0cdf451f350ece45b9968b378bb1
treef351232b2ae86451766fe26f04fa8199590a7e23
parentb983fcb585b3e2ccd28b6646269717bdb5826814
radv: fix dynamic RT stack size with VGPR spilling

VGPR spilling might cause VGPRs to be spilled at scratch offset 0, so we
can't use that.

fossil-db (Sienna Cichlid, Q2RTX and Control):
Totals from 4 (0.26% of 1524) affected shaders:
Instrs: 8734 -> 8737 (+0.03%)
CodeSize: 48492 -> 48504 (+0.02%)
Latency: 384375 -> 384369 (-0.00%)
InvThroughput: 256250 -> 256246 (-0.00%)
Copies: 1312 -> 1313 (+0.08%)
Branches: 256 -> 258 (+0.78%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18541>
src/amd/common/ac_shader_args.h
src/amd/compiler/aco_instruction_selection.cpp
src/amd/vulkan/radv_cmd_buffer.c
src/amd/vulkan/radv_pipeline_rt.c
src/amd/vulkan/radv_shader.h
src/amd/vulkan/radv_shader_args.c
src/amd/vulkan/radv_shader_info.c
src/compiler/nir/nir_divergence_analysis.c
src/compiler/nir/nir_intrinsics.py