IB/mlx5: Add MR cache for large UMR regions
authorArtemy Kovalyov <artemyko@mellanox.com>
Mon, 2 Jan 2017 09:37:44 +0000 (11:37 +0200)
committerDavid S. Miller <davem@davemloft.net>
Mon, 2 Jan 2017 20:51:20 +0000 (15:51 -0500)
commit7d0cc6edcc7011133c45f62a7796a98b8cb5da0f
tree1f6f71e23526b24f45f53aabcc32d91f192b6986
parentc438fde1c288a754aa5d22e3668f03a1dde18335
IB/mlx5: Add MR cache for large UMR regions

In this change we turn mlx5_ib_update_mtt() into generic
mlx5_ib_update_xlt() to perfrom HCA translation table modifiactions
supporting both atomic and process contexts and not limited by number
of modified entries.
Using this function we increase preallocated MRs up to 16GB.

Signed-off-by: Artemy Kovalyov <artemyko@mellanox.com>
Signed-off-by: Leon Romanovsky <leon@kernel.org>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/infiniband/hw/mlx5/main.c
drivers/infiniband/hw/mlx5/mem.c
drivers/infiniband/hw/mlx5/mlx5_ib.h
drivers/infiniband/hw/mlx5/mr.c
drivers/infiniband/hw/mlx5/odp.c
drivers/net/ethernet/mellanox/mlx5/core/main.c
include/linux/mlx5/driver.h