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armv8: fsl-layerscape: Update TZASC registers type
authorPriyanka Jain <priyanka.jain@nxp.com>
Thu, 17 Nov 2016 06:59:53 +0000 (12:29 +0530)
committerYork Sun <york.sun@nxp.com>
Tue, 22 Nov 2016 19:37:41 +0000 (11:37 -0800)
commit7cfbb4abe3c4755363aa3d692511bf187852adf6
tree17d3139b8c12529f22f81d838be2ad5b8a3dc3c0tree | snapshot
parentf6b96ff665844291a76de139bfbaa75fc0c7d917commit | diff
armv8: fsl-layerscape: Update TZASC registers type

TZASC registers like TZASC_GATE_KEEPER, TZASC_REGION_ATTRIBUTES
are 32-bit regsiters.
So while doing register load-store operations, 32-bit intermediate
register, w0 should be used.
Update x0 register to w0 register type.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S diff | blob | history
Domain: System / Kernel;