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(parent: 396bc9d) | patch
clk: renesas: r8a77990: Correct parent clock of DU
authorTakeshi Kihara <takeshi.kihara.df@renesas.com>
Fri, 12 Oct 2018 07:48:34 +0000 (16:48 +0900)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Tue, 4 Dec 2018 09:29:51 +0000 (10:29 +0100)
commit7cf3a216a2b3a672cad3e498c186c9333bdff90a
tree21d8500e3bd49df0b499dc5a5805cde560703cbbtree | snapshot
parent396bc9d40d694befa1c2c88f9873afc62a189b5fcommit | diff
clk: renesas: r8a77990: Correct parent clock of DU

According to the R-Car Gen3 Hardware Manual Rev 1.00, the parent clock
of the DU module clocks on R-Car E3 is S1D1.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Fixes: 3570a2af473789c5 ("clk: renesas: cpg-mssr: Add support for R-Car E3")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
drivers/clk/renesas/r8a77990-cpg-mssr.c diff | blob | history
Domain: System / Kernel;