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[X86] Add ROR/ROL/SHR/SAR by 1 instructions to the Sandy Bridge scheduler model.
authorCraig Topper <craig.topper@intel.com>
Tue, 20 Mar 2018 03:01:59 +0000 (03:01 +0000)
committerCraig Topper <craig.topper@intel.com>
Tue, 20 Mar 2018 03:01:59 +0000 (03:01 +0000)
commit7c90e29cf8f46d4c4de772e1e64d2620b2bbaf23
tree67f7950dc0457b1dea7a642e0136707aefb188ebtree | snapshot
parent508f68233d060987951ab1699ca9cf03110e92b0commit | diff
[X86] Add ROR/ROL/SHR/SAR by 1 instructions to the Sandy Bridge scheduler model.

I assume these match the generic immediate version like they do in the other models.

llvm-svn: 327943
llvm/lib/Target/X86/X86SchedSandyBridge.td diff | blob | history
llvm/test/CodeGen/X86/schedule-x86_64.ll diff | blob | history
Domain: System / Toolchain;