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(parent: 6f56167) | patch
tools/power/x86/intel-speed-select: Unify TRL levels
authorZhang Rui <rui.zhang@intel.com>
Sat, 20 Aug 2022 10:11:21 +0000 (18:11 +0800)
committerSrinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Wed, 22 Mar 2023 20:36:47 +0000 (13:36 -0700)
commit7c7e7c0d396b99d5b41d052dbf2b2bddcd5f7f3c
treefc417b22363928d59f8db5ee2be786b1a8136f2etree | snapshot
parent6f561677c2f234bcf215350b76f2a2fea95fbebfcommit | diff
tools/power/x86/intel-speed-select: Unify TRL levels

TRL supports different levels including SSE/AVX2/AVX512.

Avoid using hardcoded level name and structure fields, so that a loop can
be used to parse each TRL level instead. This reduces several lines of
source code.

No functional changes are expected.

Signed-off-by: Zhang Rui <rui.zhang@intel.com>
[srinivas.pandruvada@linux.intel.com: changelog edits]
Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
tools/power/x86/intel-speed-select/isst-core.c diff | blob | history
tools/power/x86/intel-speed-select/isst-display.c diff | blob | history
tools/power/x86/intel-speed-select/isst.h diff | blob | history
Domain: System / Kernel;