[PowerPC] Enable printing instructions using aliases
authorHal Finkel <hfinkel@anl.gov>
Thu, 23 Apr 2015 18:30:38 +0000 (18:30 +0000)
committerHal Finkel <hfinkel@anl.gov>
Thu, 23 Apr 2015 18:30:38 +0000 (18:30 +0000)
commit7c5cb066d091eed948d0ef10bb15b9def37b81ab
tree0e373508c363bd3b312a69e8dd4dbf71a6afaa12
parent9cf4f2c2d8347c9e7843ac4c00854ca0eb386ac1
[PowerPC] Enable printing instructions using aliases

TableGen had been nicely generating code to print a number of instructions using
shorter aliases (and PowerPC has plenty of short mnemonics), but we were not
calling it. For some of the aliases we support in the parser, TableGen can't
infer the "inverse" alias relationship, so there is still more to do.

Thus, after some hours of updating test cases...

llvm-svn: 235616
55 files changed:
llvm/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp
llvm/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h
llvm/test/CodeGen/PowerPC/2007-01-15-AsmDialect.ll
llvm/test/CodeGen/PowerPC/2010-02-12-saveCR.ll
llvm/test/CodeGen/PowerPC/anon_aggr.ll
llvm/test/CodeGen/PowerPC/asm-constraints.ll
llvm/test/CodeGen/PowerPC/atomic-2.ll
llvm/test/CodeGen/PowerPC/atomics-fences.ll
llvm/test/CodeGen/PowerPC/atomics-indexed.ll
llvm/test/CodeGen/PowerPC/atomics.ll
llvm/test/CodeGen/PowerPC/bperm.ll
llvm/test/CodeGen/PowerPC/cmpb-ppc32.ll
llvm/test/CodeGen/PowerPC/cmpb.ll
llvm/test/CodeGen/PowerPC/compare-simm.ll
llvm/test/CodeGen/PowerPC/crbit-asm.ll
llvm/test/CodeGen/PowerPC/crbits.ll
llvm/test/CodeGen/PowerPC/cttz.ll
llvm/test/CodeGen/PowerPC/fast-isel-cmp-imm.ll
llvm/test/CodeGen/PowerPC/fast-isel-conversion.ll
llvm/test/CodeGen/PowerPC/fast-isel-ext.ll
llvm/test/CodeGen/PowerPC/i64_fp_round.ll
llvm/test/CodeGen/PowerPC/long-compare.ll
llvm/test/CodeGen/PowerPC/ppc32-cyclecounter.ll
llvm/test/CodeGen/PowerPC/ppc64-zext.ll
llvm/test/CodeGen/PowerPC/rlwimi-and.ll
llvm/test/CodeGen/PowerPC/rotl-2.ll
llvm/test/CodeGen/PowerPC/rotl-64.ll
llvm/test/CodeGen/PowerPC/rotl.ll
llvm/test/CodeGen/PowerPC/sdag-ppcf128.ll
llvm/test/CodeGen/PowerPC/seteq-0.ll
llvm/test/CodeGen/PowerPC/stack-realign.ll
llvm/test/CodeGen/PowerPC/subreg-postra-2.ll
llvm/test/CodeGen/PowerPC/subreg-postra.ll
llvm/test/CodeGen/PowerPC/vsx-ldst-builtin-le.ll
llvm/test/CodeGen/PowerPC/vsx-ldst.ll
llvm/test/CodeGen/PowerPC/vsx.ll
llvm/test/CodeGen/PowerPC/vsx_insert_extract_le.ll
llvm/test/CodeGen/PowerPC/vsx_shuffle_le.ll
llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-4xx.txt
llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-bookII.txt
llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-bookIII.txt
llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ext.txt
llvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt
llvm/test/MC/Disassembler/PowerPC/ppc64-operands.txt
llvm/test/MC/Disassembler/PowerPC/qpx.txt
llvm/test/MC/Disassembler/PowerPC/vsx.txt
llvm/test/MC/PowerPC/ppc64-encoding-4xx.s
llvm/test/MC/PowerPC/ppc64-encoding-6xx.s
llvm/test/MC/PowerPC/ppc64-encoding-bookII.s
llvm/test/MC/PowerPC/ppc64-encoding-bookIII.s
llvm/test/MC/PowerPC/ppc64-encoding-ext.s
llvm/test/MC/PowerPC/ppc64-encoding-fp.s
llvm/test/MC/PowerPC/ppc64-encoding.s
llvm/test/MC/PowerPC/qpx.s
llvm/test/MC/PowerPC/vsx.s