arm64: dts: renesas: Add initial DTSI for RZ/V2L SoC
authorBiju Das <biju.das.jz@bp.renesas.com>
Mon, 10 Jan 2022 13:46:57 +0000 (13:46 +0000)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Wed, 2 Feb 2022 08:23:23 +0000 (09:23 +0100)
commit7c2b8198f4f321df03e285a931fab2a33668c88d
treec28bdbf1636a9b4ce24393a435382dee8c26a090
parent4a3680d038404d8e97c059119f344fa53c19de25
arm64: dts: renesas: Add initial DTSI for RZ/V2L SoC

The RZ/V2L SoC is package- and pin-compatible with RZ/G2L, the only
difference being that the RZ/V2L SoC has additional DRP-AI IP (AI
accelerator).

Add initial DTSI for the RZ/V2L SoC with below SoC specific dtsi files
for supporting single core and dual core devices:

    r9a07g054l1.dtsi => RZ/V2L R9A07G054L1 SoC specific parts
    r9a07g054l2.dtsi => RZ/V2L R9A07G054L2 SoC specific parts

Both the RZ/G2L and RZ/V2L SMARC EVK SoMs are identical apart from the
SoCs used, hence the common dtsi files (rzg2l-smarc*.dtsi) are shared
between the RZ/G2L and RZ/V2L SMARC EVKs.  Place holders are added in
device nodes to avoid compilation errors for devices which have not been
enabled yet on the RZ/V2L SoC.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220110134659.30424-11-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
arch/arm64/boot/dts/renesas/r9a07g054.dtsi [new file with mode: 0644]
arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi [new file with mode: 0644]
arch/arm64/boot/dts/renesas/r9a07g054l2.dtsi [new file with mode: 0644]