clk: rockchip: add new pll-type for rk3328
authorElaine Zhang <zhangqing@rock-chips.com>
Thu, 29 Dec 2016 02:45:10 +0000 (10:45 +0800)
committerHeiko Stuebner <heiko@sntech.de>
Mon, 2 Jan 2017 13:24:57 +0000 (14:24 +0100)
commit7bed92460d910c75f0d722f1240d2dc1d466d884
treebd93e4e945478ec6a7806d1856788dd5b2ae8d33
parent4d3e84f9962800fb355e1c10e57e998ae574efa2
clk: rockchip: add new pll-type for rk3328

The rk3328's pll and clock are similar with rk3036's,
it different with pll_mode_mask, the rk3328 soc
pll mode only one bit(rk3036 soc have two bits)
so these should be independent and separate from
the series of rk3328s.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
drivers/clk/rockchip/clk-pll.c
drivers/clk/rockchip/clk.h