i965/disasm: Improve render target write message disassembly.

i965/disasm: Improve render target write message disassembly.

Previously, we decoded render target write messages as:

   render ( RT write, 0, 16, 12, 0) mlen 8 rlen 0

which made you remember (or look up) what the numbers meant:

1. The binding table index
2. The raw message control, undecoded:
   - Last Render Target Select
   - Slot Group Select
   - Message Type (SIMD8, normal SIMD16, SIMD16 replicate data, ...)
3. The dataport message type, again (already decoded as "RT write")
4. The write commit bit (0 or 1)

Needless to say, having to decipher that yourself is annoying.  Now, we
do:

   render RT write SIMD16 LastRT Surface = 0 mlen 8 rlen 0

with optional "Hi" and "WriteCommit" for slot group/write commit.

Thanks to the new brw_inst API, we can also stop duplicating code on a
per-generation basis.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>