AMDGPU: Add definitions for scalar store instructions
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Fri, 28 Oct 2016 21:55:15 +0000 (21:55 +0000)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Fri, 28 Oct 2016 21:55:15 +0000 (21:55 +0000)
commit7b6475568d8449dd84ddc839181cfc0ac74a3e13
tree5a159d350f597786e65d0059e94937d99b277e13
parent4b6a6cc8e994fb0e4b0790816ecdd89a44080863
AMDGPU: Add definitions for scalar store instructions

Also add glc bit to the scalar loads since they exist on VI
and change the caching behavior.

This currently has an assembler bug where the glc bit is incorrectly
accepted on SI/CI which do not have it.

llvm-svn: 285463
llvm/lib/Target/AMDGPU/AMDGPU.td
llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
llvm/lib/Target/AMDGPU/SIDefines.h
llvm/lib/Target/AMDGPU/SIInstrFormats.td
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/lib/Target/AMDGPU/SIInstrInfo.h
llvm/lib/Target/AMDGPU/SMInstructions.td
llvm/test/CodeGen/AMDGPU/coalescer-subreg-join.mir
llvm/test/CodeGen/MIR/AMDGPU/target-index-operands.mir
llvm/test/MC/AMDGPU/smem.s
llvm/test/MC/AMDGPU/smrd-err.s