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author	Monk Chiang <monk.chiang@sifive.com>
	Wed, 30 Nov 2022 09:07:14 +0000 (17:07 +0800)
committer	Monk Chiang <monk.chiang@sifive.com>
	Wed, 7 Dec 2022 06:14:15 +0000 (22:14 -0800)
commit	7b50c183601adf8cacf20f3644cb0f72c7cd1125
tree	bc494f24abadd40d9a359e716ac6c4275744e8f7	tree \| snapshot
parent	d42c76aba0f4465cd4ae4ed0c0cc64d141cdf476	commit \| diff

[RISCV] Codegen support for Zfhmin.

The Zfhmin subset only has FLH, FSH, FMV.X.H, FMV.H.X, FCVT.S.H, and FCVT.H.S.
If the D extension is present, the FCVT.D.H and FCVT.H.D instructions are also included.
Since most instructions are not included for Zfhmin, so most operations are promoted.
The patch primarily about making f16 a legal type.

RISC-V ISA info:
https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D139391

31 files changed:

llvm/lib/Target/RISCV/RISCV.td		diff \| blob \| history
llvm/lib/Target/RISCV/RISCVISelLowering.cpp		diff \| blob \| history
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp		diff \| blob \| history
llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td		diff \| blob \| history
llvm/lib/Target/RISCV/RISCVSubtarget.h		diff \| blob \| history
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h		diff \| blob \| history
llvm/test/CodeGen/RISCV/calling-conv-half.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/copysign-casts.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/half-arith-strict.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/half-arith.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/half-br-fcmp.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/half-convert-strict.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/half-convert.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/half-fcmp-strict.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/half-fcmp.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/half-frem.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/half-imm.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/half-intrinsics.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/half-isnan.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/half-mem.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/half-round-conv-sat.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/half-round-conv.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/half-select-fcmp.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/half-select-icmp.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rv64zfhmin-half-convert-strict.ll	[new file with mode: 0644]	blob
llvm/test/CodeGen/RISCV/rv64zfhmin-half-convert.ll	[new file with mode: 0644]	blob
llvm/test/CodeGen/RISCV/rv64zfhmin-half-intrinsics.ll	[new file with mode: 0644]	blob
llvm/test/CodeGen/RISCV/zfhmin-half-intrinsics-strict.ll	[new file with mode: 0644]	blob
llvm/test/CodeGen/RISCV/zfhmin-half-intrinsics.ll	[new file with mode: 0644]	blob
llvm/test/CodeGen/RISCV/zfhmin-imm.ll	[new file with mode: 0644]	blob

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