drm/i915/icl: Get DDI clock for ICL for MG PLL and TBT PLL
authorManasi Navare <manasi.d.navare@intel.com>
Fri, 17 Aug 2018 21:52:09 +0000 (14:52 -0700)
committerPaulo Zanoni <paulo.r.zanoni@intel.com>
Mon, 20 Aug 2018 21:38:41 +0000 (14:38 -0700)
commit7b19f544ed90b7ca4bd850145e2624a99a967de0
tree6e3fe234c942973c781400ea3e298cfa3f3ca614
parentbcaad532974eb47f1fb4ee04ede9812107060245
drm/i915/icl: Get DDI clock for ICL for MG PLL and TBT PLL

PLLs are the source clocks for the DDIs so in order to determine the
ddi clock we need to check the PLL configuration.

For MG PHy Ports (C - F), depending on whether it is a TBT PLL or MG
PLL the link lock can be obtained from the the PLL divisors based on
the specification.

v2 (from Paulo):
 * Make the algorithm look more like what's in the spec, also document
   where we differ form the spec and why.
 * Make the code a little more consistent with our coding style.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180817215209.29133-2-paulo.r.zanoni@intel.com
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_ddi.c