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[RISCV] Add more sign-extending ops to MIR sext.w pass.
authorMohammed Nurul Hoque <mohammed.nurulhoque@imgtec.com>
Fri, 18 Mar 2022 09:26:10 +0000 (17:26 +0800)
committerKito Cheng <kito.cheng@sifive.com>
Fri, 18 Mar 2022 10:21:17 +0000 (18:21 +0800)
commit7afa44f5f57e6f3ccf8717a76073126d489c0ef8
treeef0520031099c41958ad8d96fef7915252da54fftree | snapshot
parent53491e451962a9ba272d59da45bf7f43db73c563commit | diff
[RISCV] Add more sign-extending ops to MIR sext.w pass.

This patch adds single-bit and bit-counting ops to list of sign-extending ops.

A single-bit write propagates sign-extendedness if it's not in the sign-bits.

Bit extraction and bit counting always outputs a small number, so sign-extended.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D121152
llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp diff | blob | history
llvm/test/CodeGen/RISCV/sextw-removal.ll diff | blob | history
Domain: System / Toolchain;