drm/i915/icl: Add VIDEO_DIP registers
authorAnusha Srivatsa <anusha.srivatsa@intel.com>
Tue, 17 Jul 2018 21:10:58 +0000 (14:10 -0700)
committerRodrigo Vivi <rodrigo.vivi@intel.com>
Thu, 19 Jul 2018 00:47:33 +0000 (17:47 -0700)
commit7af2be6d54d4eda52603e87fbb99a8fb989ccdf0
tree5f5b648d679ac374f53455197d46b25c99d01711
parent5fd9df6ac6eec9d6c7feaf114690bbeac7f13168
drm/i915/icl: Add VIDEO_DIP registers

The Picture Parameter Set metadata for DSC has to be sent
to the panel through secondary data packets. Add the error
correction registers, data registers and control registers
for the same.

The control registers for  transcoders A and B are already
defined and will be reused for Icelake purpose. This patch adds
Control register for EDP and transcoder C apart from adding the
PPS data and error registers.

v2: reuse MMIO_TRANS2 for _PPS_DATA and _PPS_ECC.
The  _MMIO_TRANS2(pipe, reg) macro definition takes care of the eDp case

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1531861861-10950-1-git-send-email-anusha.srivatsa@intel.com
drivers/gpu/drm/i915/i915_reg.h