clk:starfive:Add PLL2 frequency controller
authorxingyu.wu <xingyu.wu@starfivetech.com>
Fri, 15 Jul 2022 03:53:25 +0000 (11:53 +0800)
committerxingyu.wu <xingyu.wu@starfivetech.com>
Wed, 20 Jul 2022 08:48:00 +0000 (16:48 +0800)
commit7ab7898ae6ccd44551acd1cde1cc7a6b5039f6b4
tree9d38e225ba085ca430389b9a9aeba1b10f064f24
parent30eb809e182f1fcfa797f60f9e622ac037486b19
clk:starfive:Add PLL2 frequency controller

If enable CONFIG_CLK_STARFIVE_JH7110_PLL, also could read or set PLL1 clock's
rate by reading or setting syscon registers.

Signed-off-by: xingyu.wu <xingyu.wu@starfivetech.com>
drivers/clk/starfive/clk-starfive-jh7110-gen.c
drivers/clk/starfive/clk-starfive-jh7110-pll.c
drivers/clk/starfive/clk-starfive-jh7110-pll.h
drivers/clk/starfive/clk-starfive-jh7110-sys.c